Integrated circuit designs are continually being scaled down in efforts to reduce power consumption and increase speed. With each passing generation, devices tend to get smaller and more densely packed, raising a variety of problems for integration. One of the problems for integration is the small volumes provided for conductive elements. In order to achieve acceptable circuit speeds, it is important that such elements are provided with very high conductivity.
Other problems relate to difficulties in lining or filling high aspect ratio trenches or vias. For example, elongated trenches are used for damascene metallization; isolated holes or vias are used for forming vertical contacts; stacked trenches above the substrate and deep trenches within the substrate are used for memory cell capacitor formation; etc. Depositing within such vias becomes more challenging with higher aspect ratios with each passing generation. Voids can easily form during deposition or subsequent processing, leading to lower device yields.